Seriales house of cards

By | June 26, 2019

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seriales house of cards

Next Steps 1. The Emergence of High-Speed Serial Interfaces With the ever-increasing demand for higher data bandwidth, wired interfaces have increased their clock rates and parallelism to keep up. However, with traditional parallel data buses, the smallest amount of skew between the clock and data lines can threaten the bit error rate of the interface.

Serial data links offer a solution to this issue by embedding the clock into the data stream of a given pair of differential traces, which eliminates the possibility of skew between the clock and the data. This requires additional electronics at the receiving end of the interface as well as additional encoding for clock recovery; however, it makes dramatically higher data rates possible, which satisfies the demand for bandwidth. Figure 1.

Parallel clock black and data blue versus embedded clock in data red , with equivalent data bandwidth. For design and test engineers, validating these interfaces presents new challenges that require new test hardware. Traditionally, engineers have used expensive oscilloscopes or bit error rate testers BERTs to characterize the physical interfaces and have used protocol-specific analyzers and generators to validate that the protocol stack is implemented correctly and that data transmission and reception operate efficiently.

Oscilloscopes and bit error rate testers are often too expensive and slow to justify the coverage they provide, while protocol-specific hardware is often not flexible enough to integrate into automated test systems. Because it is protocol-specific, the hardware cannot be reused for other tests or repurposed for other devices under test DUTs.

FPGAs provide a solution for these challenges. Apart from this, however, they are similar. Figure 2. PXIe hardware architecture with key interfaces and data rates. With up to 24 lanes at They use current mode logic CML , which is a differential interface that features a small signal swing of mVpp nominally, mVpp max. All high-speed serial interfaces require a reference clock that operates at an integer divisor of the line rate. For maximum flexibility, the GTX transceivers include a phase-locked loop PLL that can multiply the reference clock up to times to produce the serial data rate.

They also include serial-to-parallel and parallel-to-serial converters with ratios up to 80x, limiting FPGA clock frequencies while enabling high serial data rates. In addition to providing the high-speed serial transceivers, the Xilinx FPGAs on the instruments serve a number of other vital purposes. They implement the logic for the protocol in use, as well as any application-specific user logic for hardware configuration and data generation, reception, and movement throughout the system.

Both FPGAs provide ample resources for a wide variety of high-performance applications. A low-jitter, high-fidelity reference clock is a critical component of any high-speed serial communications system. The PXIe and PXIe feature front panel coaxial connectivity for exporting the built-in reference clock, and all three modules have connectivity for importing an external reference clock.

Active optical cables AOCs are also available in lengths up to and beyond meters. The cables perform electrical-to-optical and optical-to-electrical conversion in the connector housing. Because these cables are factory-terminated, there are generally fewer length options when compared to other fiber-optic connectivity solutions. In addition, they cannot be terminated in the field.

These connectors work with a variety of serial protocols and offer very high density, which leaves room for other connectivity on the front panel of the module. The user-programmable FPGA controls these signals to implement application-specific functionality. Each connector includes a single differential TX and RX channel. However, they may also carry other serial protocols.

Optical transceiver modules are available for a variety of wavelengths of light, as well as single and multi-mode fibers. These, however, incorporate additional circuitry to convert to the pulse amplitude modulated signals used by Gigabit Ethernet. An additional feature on the PXIe is a second, fixed reference clock at Software A software-designed instrument provides the same functionality as a fixed-function instrument, but users can customize the instrumentation hardware through an open, user-programmable FPGA.

As such, there is no single high-level API for programming these devices. To help users get up and running quickly, a multitude of examples demonstrate the use of different protocols, as well as different use models for these instruments. A software-designed instrument provides the same functionality as a fixed-function instrument, but users can customize the instrumentation hardware through an open, user-programmable FPGA The open FPGA provides a degree of customization not found in other instruments.

First and foremost, it implements the serial protocol for which the instrument is configured. Beyond just the protocol, user-defined hardware functionality allows types of tests not previously possible.

For instance, algorithmic data generation on the FPGA reduces the required waveform storage memory and system bandwidth for downloading these waveforms, which accelerates test throughput. Algorithmic data analyses such as response comparison, intelligent triggering, and data reduction and compression drastically reduce the amount of data for the host CPU to process, which also decreases test time.

It also enables custom compression and decompression algorithms, which allows for optimal use of DRAM size and bandwidth. Finally, user-defined data movement to and from the PXIe, PXIe, or PXIe and the host or other instruments delivers significant flexibility for system-level integration.

For example, it is possible to convert analog data to digital samples with a high-speed digitizer, use NI P2P streaming to transfer that data to a high-speed serial instrument at rates up to 3. Alternatively, a high-speed serial instrument can capture a serial data stream and transfer it to the host CPU and ultimately a high-bandwidth RAID array for hours or even days of continuous storage, again at rates up to 3.

GTX transceiver configuration is generally protocol-specific and IP already exists for many high-speed serial interfaces either HDL or netlist with built-in transceiver configuration. Figure 6. Beyond defining the logic to be implemented on the user-programmable FPGA, LabVIEW simplifies hardware configuration through its project hierarchy and the associated configuration pages.

For example, the reference clock configuration on these high-speed serial instruments requires a complex algorithm to determine hundreds of register settings to be applied to as many as four separate integrated circuits, in addition to the logic required to apply these registers when the FPGA powers on. LabVIEW FPGA exposes this as a dialog box with a graphical representation of the options, and design rules and guidance to enforce valid configurations. This simplifies the configuration of the any-rate clock synthesizer and routing circuitry to a task that takes minutes rather than hours or days.

Figure 7. The Instruction Framework is an instrument design library for dynamic hardware configuration during run time. Though most hardware functionality of these serial instruments for example, clock configuration can be statically configured in the LabVIEW project, users can take advantage of the Instruction Framework to control application-specific firmware parameters.

Figure 8. The Xilinx GTX transceivers feature two receiver comparators per channel. While one comparator automatically tracks the center of the serial eye based on the recovered clock frequency and phase, the other comparator can independently shift in amplitude and phase.

By varying the parameters of the latter comparator and comparing the results with that of the former, the Eye Scan instrument design library can create a statistical eye diagram useful for determining the link margin of the interface, accurate to the bit error rate floor of the Xilinx GTX transceivers. Furthermore, because the Eye Scan instrument design library uses an independent set of hardware resources, it can coexist with other protocol IP and run simultaneously with other application-specific functionality.

Figure 9. Beyond these instrument design libraries, other NI software-designed instruments provide libraries for a variety of useful functions such as multi-record, DRAM-based acquisition and generation. Figure Engineers can use the DSP instrument design library to synthesize a sinusoid for a transmission to a digital to analog converter over the serial JESDB protocol.

NI provides a number of software examples to demonstrate how to integrate common protocols, as well as LabVIEW architectures for several application patterns. Each example comes with a precompiled FPGA bitfile for the supported instrument, along with the associated source code and protocol IP.

This protocol IP is available for purchase either through Xilinx or resellers such as Avnet or Digikey. Xilinx Aurora Xilinx Aurora provides a lightweight, low-latency, small-footprint protocol designed for serial point-to-point interfaces. It supports the full rate of the Xilinx GTX serial transceivers, as well as lane bonding for even greater bandwidth.

Primarily designed for high-bandwidth data movement, Aurora provides flow control, flexible framing, and options for simplex or full-duplex channels. More information on Xilinx Aurora is at the following links:

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